1. Field of the Invention
Embodiments of the present invention relate to semiconductor fabrication, and in particular, to methods for obtaining submicron semiconductor device geometries by trimming layers of a structure used in the patterning of an underlying structure.
2. Background Technology
Current semiconductor manufacturing uses a variety of techniques to achieve sub-100 nm gate line widths.
FIG. 1 shows a structure used in the formation of a MOSFET gate line in a conventional process. The structure includes a semiconductor substrate 2 having field oxides 4 that bound source/drain regions of a MOSFET. Layers of a gate insulating material 6 such as silicon oxide and a gate conductive material 8 such as doped polysilicon are formed over the substrate. Formed over the gate conductive layer 8 is a multi-layer hardmask/antireflective coating (ARC) structure including an amorphous carbon layer 10 and an antireflective layer 12 such as silicon carbide, silicon nitride, silicon oxide, silicon oxynitride, SiROx, or SiRN. A photoresist mask 14 for defining the pattern of the gate is formed on the antireflective layer 12. In conventional processing, a first etch is used to transfer the photoresist mask pattern to the antireflective layer 12, a second etch is used to transfer the antireflective layer 12 mask pattern to the amorphous carbon layer 10, a third etch is used to transfer the amorphous carbon layer 10 mask pattern to the polysilicon gate conductive layer 8, a fourth etch is used to remove oxide from the surface of the patterned polysilicon gate conductive layer, and further etches are performed to pattern the underlying gate insulating layer.
One technique for reducing the size of features patterned in this manner involves trimming the photoresist mask by subjecting it to an isotropic etch prior to patterning of underlying layers. This reduces the width of the mask and therefore the width of the pattern that it transfers to the underlying layer. For example, in FIG. 1 the photoresist mask may be trimmed from its original size 14a to a reduced size 14b. This technique enables reduction of the size of the mask to less than the minimum feature size that can be created in the photoresist material solely through projection lithography.
A disadvantage of the photoresist trim technique is that it becomes more difficult to perform as device dimensions are reduced. Too much trimming leaves too thin a photoresist mask, such that subsequent degradation of the photoresist material during patterning of the underlying layer leads to errors in pattern transfer. While this may be addressed to some extent by using a thicker photoresist layer, too thick a photoresist layer will result in a structure that may be too narrow to support its own height and thus may collapse or fall over.
Consequently, there is a need for supplemental or alternative techniques for reducing semiconductor device geometries.